The present invention relates to a sampling pulse generator for generating a sampling pulse for sampling a character signal on a television signal.
In a character/TV signal multiplex broadcasting system, character information is transmitted from a broadcasting station to a receiving end, using the television signal, and this character information is reproduced at the receiving end. The character information is superimposed as the character signal during a predetermined horizontal scan period of a vertical blanking period.
The character signal comprises a clock run-in signal, a framing code, and a data portion including the actual character data and control data. The clock run-in signal indicates a reference phase of the character signal. The framing code is used for frame synchronization.
A character/TV signal multiplex reception apparatus separates the character signal from the television signal. The separated character signal is sampled and written in a buffer memory. Predetermined processing is performed for the data written in the buffer memory, thereby obtaining picture data to be supplied to a CRT monitor.
The sampling pulse for sampling the character signal has a frequency (8/5)f.sub.SC (where f.sub.SC is the frequency of the chrominance subcarrier signal) which is the same as the bit rate of the character signal. The sampling pulse is generally prepared by synchronizing a free run pulse also having a frequency of (8/5)f.sub.SC to the clock run-in signal.
A sampling generator shown in the text book used at the conference of the Insititute of Television Engineers' of Japan; the Character TV broadcasting & CAPTAIN system, (4) A receiver for the character TV broadcasting, (June 16-17, 1981) is used to generate the above-mentioned sampling pulse. This sampling pulse generator has a 5-stage ring counter. This ring counter is driven by a clock pulse having a frequency of 8f.sub.SC (one period: 35 nsec). Therefore, the frequency of a count output from the ring counter is the same as that [(4/5 f.sub.SC ] (one period: 350 nsec) of the clock run-in signal. The count output is doubled to obtain a pulse having a frequency equal to that [(8/5)f.sub.SC ] (one period: 175 nsec) of the sampling pulse. In order to use the doubled output as the sampling pulse, the counting operation of the ring counter is phase-corrected to be synchronized with the clock run-in signal. This can be performed by shifting the phase of the count output in units of one period (35 nsec) of the clock run-in signal.
However, the following problem is present in the sampling pulse generator described above. The phase of the character signal is discrete throughout each horizontal scan period. The phase is shifted within a range of about .+-.0.35 .mu.sec. When the phase of the clock run-in signal (CR) is shifted, phase correction as described above is performed. Therefore, the phase of the count output from the ring counter is shifted in units of 35 nsec, and hence the phase of the sampling pulse is also shifted in units of 35 nsec. In other words, the sampling pulse has jitter of 35 nsec. Since the jitter of the sampling pulse results in an error of sampled data, it must be as small as possible. For example, even if a change in phase of the clock run-in signal is small, the phase of the pulse is shifted by 35 nsec. As a result, the character signal cannot be sampled at an optimum sampling phase.
In order to prevent this problem, it is proposed that the frequency of the clock signal for driving the ring counter be made higher than 8f.sub.SC. However, it is undesirable to increase the frequency of the clock signal from the viewpoint of the operating speed of the circuit elements. Furthermore, when the frequency of the clock signal is increased, the number of stages of the ring counter must be increased. As a result, when a phase difference between the clock run-in signal and the count output from the ring counter is great, phase correction cannot be completed within the period of the clock run-in signal.